A common requirement for semiconductor processing and advanced packaging of integrated circuit is assembly of integrated circuit dies to a substrate to form a completed device. The integrated circuit dies typically include active and passive circuit devices, such as transistors and capacitors, fabricated in a semiconductor process. A plurality of connector terminals are formed on the active surface of the integrated circuit dies. The assembly of the dies to the substrates requires that the integrated circuit dies be separated from a semiconductor wafer; the integrated circuit die is then mounted with the respective connector terminals forming electrical and physical connections to corresponding pads or lands on a substrate.
In the conventional assembly process, “flip chip” bonding is performed. Individual integrated circuit dies are fabricated on a semiconductor wafer in a semiconductor process. The dies are then separated from a semiconductor wafer by a wafer dicing or “singulation” process. The integrated circuit dies are then removed from a wafer mount tape or other support by a “pick and place” tool. The substrate has lands or pads configured to align with the integrated circuit die connector terminals. The two pieces are aligned and then brought together in physical contact and then the solder reflow process is used to electrically and physically couple the connector terminals of the integrated circuit to the pads on the substrate.
In the known flip chip approaches, several problems are encountered. Alignment of the integrated circuit die, which is carried in a “flipped” position by a bonding tool with the substrate, which is positioned face up and disposed beneath the integrated circuit die, is difficult and takes several steps. Several separate optical lenses are used, such as charge coupled device (CCD) optical sensors or cameras, to align the two pieces prior to bonding. In order to achieve precise alignment the component carrying head, the substrate carrying tool, or both, may move back and forth several times, substantially slowing the throughput for the chip attach process. Component alignment and bonding to the substrate limits the maximum throughput that may be achieved, increasing per unit costs.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the disclosure, are simplified for explanatory purposes, and are not drawn to scale.